Focal plane array technology incorporating very small pixel detector sizes (i.e., less than about five microns) poses significant technical challenges. Challenges include those related to the integration of readout integrated circuits (ROIC) for use in mega-pixel sized arrays. Small pixel sizes and large focal plane arrays are difficult to realize from both the electronic and detector sensitivity aspects.
Certain classes of focal plane array detectors and photon detectors desirably separate the photon-electron conversion process from the electronic readout circuitry in such a way as to enable very small circuit geometries. This technology can provide low-cost, high performance, mega-pixel imagers for applications in security and law enforcement and is applicable to military uses in reconnaissance, space, weapons sights, multi-purpose imaging, missile threat warning, chemical and biological detection and the like.
The major technical challenges in the field of focal plane array technology are detector size, readout integrated circuit electronics size, detector materials, detector sensitivity/quantum efficiency, electronics noise, speed and dynamic range; all of which are optimized by the electronic module disclosed herein.
The disclosed invention mitigates the conflict between pixel size and available electronics real estate within the pixel boundaries by partitioning electronics into multiple layers in a three-dimensional stack of integrated circuit chips.